Pls debug this vhdl code for a digital integrator

[pratyush23]

I m trying to work on a digital integrator..i have the verilog code of the integrator as follows...

module dig_int(output reg y, input x,clock);
reg z='b0;

always @(x,z)
y=x+z;

always @(posedge clock)
z<=y;

endmodule

i used x-hdl to convert it to a vhdl equivalent..and the code generated was as follows...


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY dig_int IS
PORT (
y : OUT STD_LOGIC;
x : IN STD_LOGIC;
clock : IN STD_LOGIC
);
END dig_int;

ARCHITECTURE trans OF dig_int IS

SIGNAL z : STD_LOGIC := '0';
SIGNAL y_xhdl0 : STD_LOGIC;

BEGIN

y <= y_xhdl0;

PROCESS (x, z)
BEGIN
y_xhdl0 <= x + z;
END PROCESS;

PROCESS (clock)
BEGIN
IF (clock'EVENT AND clock = '1') THEN
z <= y_xhdl0;
END IF;
END PROCESS;


END trans;

on synthesis of the above vhdl code, there is an error in the line
y_xhd10 <= x + z;

please suggest as to how to rectify the above problem..or any other prb so that the code can be run error-free

thanks.

 

[FvM]

In my opinion, x-hdl is a powerful tool, but can't be reasonably used without sufficient language knowledge. Some manual editing is often required.

When getting compiler errors, you should be able to understand their meaning, otherwise I don't see how you want to work with the language.

The problem revealed in the translated VHDL code is however already present in the Verilog code. You need to define numeric data types (bit vectors) with a specific bit width. Now your design has only a single bits. So the first step should be to decide about intended number format.

As a side remark, I don't see any purpose of having two always blocks. The below code will do the trick (together with suitable data types).

always @(posedge clock)
z<=x+z;

Although not provided by line-by-line x-hdl translation, the VHDL design should use ieee.numeric_std and unsigned signals.