Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

pll for ddr3 apps- how to decide the reference frequency?

Status
Not open for further replies.
amit.dounde

amit.dounde

Junior Member level 1
Joined
Jan 5, 2009
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,384
question on pll

i am implementing a pll for ddr3 apps. the vco freq range is 100-800Mhz. how do i decide the reference frequency?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top