PLL feedback divider question

[gggould]

Hi all,

Lets say the feedback divider is in div2 mode.

1.If feedback divider input is 1GHz fundmental + 1.01GHz spur,
then what does feedback divider output spectrum look like??

2.If feedback divider generates 1ps jitter,
then how does this jitter being transfer to PLL output??

Thanks

 

[D.A.(Tony)Stewart]

Dividers inside feedback loop multiply VCO output frequency , and multiply phase noise.
Dividers outside the loop simply divide both frequency and phase noise of source but with added noise of divider.