buenos
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PLL delay
hi
is there a way to phase lock the PLL input to its output when using the PLL for frequency multiplication?
can we guarante the input and output edges to be in a fixed relationship in the aspect of static timing?
does it depend on the PLL or FPGA chip, or we never can lock it?
I am asking this to figure out if it is really necessary to use asynchronous FIFOs for SERDES transmitters.
hi
is there a way to phase lock the PLL input to its output when using the PLL for frequency multiplication?
can we guarante the input and output edges to be in a fixed relationship in the aspect of static timing?
does it depend on the PLL or FPGA chip, or we never can lock it?
I am asking this to figure out if it is really necessary to use asynchronous FIFOs for SERDES transmitters.