Please Help in data conversion

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i designed a VHDL module in obtaining signal from GPIO of DE2 board (a serial input).
The code is as below.
I tried to store the shift register value (where the 16 bits input signal is shifting in) into an array in order to separate and make it parallel output(1 bit per output pin to transfer to DSP).
However, i failed to convert the data type. Even i use the conv_interger.

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;


entity new1 is
port(C, SI,busy : in std_logic;
SO : out std_logic);
end new1;
architecture archi of new1 is
signal tmp: std_logic_vector(15 downto 0);
TYPE dataout IS ARRAY(0 to 15) of bit;
signal st : integer range 0 to 15;
begin
process (C)
begin
if (C'event and C='1') then
if rising_edge(busy) then
st <= st + 1;
end if;
for i in 0 to 14 loop
tmp(i+1) <= tmp(i);
end loop;

tmp(0) <= SI;
end if;
if st = 15 then
dataout <= conv_integer(tmp); --------------- error
dataout(0) <= tmp(0);
dataout(1) <= tmp(1);
dataout(2) <= tmp(2);
dataout(3) <= tmp(3);
dataout(4) <= tmp(4);
dataout(5) <= tmp(5);
dataout(6) <= tmp(6);
dataout(7) <= tmp(7);
dataout(8) <= tmp(8);
dataout(9) <= tmp(9);
dataout(10) <= tmp(10);
dataout(11) <= tmp(11);
end if;
end process;

SO <= tmp(15);

end archi;




the location of error above showed this mesg:
- name" dataout" must represent signal

-Error (10511): VHDL Qualified Expression error at new1.vhd(28): CONV_INTEGER type specified in Qualified Expression must match dataout type that is implied for expression by context



Can anyone suggest me a solution?
Thanks





As this is the serial output in std_logic, do anyone has any idea how to assign these 16 bits in 1 complete into 16 separate output where each only consists of 1 bit according to the order (I am doing the serial in parallel out conversion to assign these parallel output bits to parallel in DSP)

Added after 1 hours 8 minutes:

Original design is as following and it is working:
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
LIBRARY work;

entity new1 is
port(C, SI, busy : in std_logic;
SO : out std_logic );
end new1;

architecture archi of new1 is
signal tmp: std_logic_vector(15 downto 0);

begin
process (C)
begin
if (C'event and C='1') then

for i in 0 to 14 loop
tmp(i+1) <= tmp(i);
end loop;

tmp(0) <= SI;
end if;
end process;

SO <= tmp(15);

end archi;

I tried to modify it to suit my application but fail. Anybody has any idea? Please help. Thanks