AlinParcalab
Newbie level 4
Here is my Verilog Code, I am tring to make a 32x32 sequential multiplier, 32 stages, here is one of the verision I have tried the other has the comblogic made out of always blocs and each odd stage is on negedge and the others are on posedge
Help please
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 module mul_piped #(parameter word = 32, parameter double = 64) ( input signed [31:0] Multiplicand, input signed [31:0] Multiplier, input clk, output signed [double-1:0] Pord ); reg [word-1:0] St1_Muld,St2_Muld,St3_Muld,St4_Muld; reg [word-1:0] St5_Muld,St6_Muld,St7_Muld,St8_Muld; reg [word-1:0] St1_Muli,St2_Muli,St3_Muli,St4_Muli; reg [word-1:0] St5_Muli,St6_Muli,St7_Muli,St8_Muli; reg [word-1:0] St9_Muld,St10_Muld,St11_Muld,St12_Muld; reg [word-1:0] St13_Muld,St14_Muld,St15_Muld,St16_Muld; reg [word-1:0] St9_Muli,St10_Muli,St11_Muli,St12_Muli; reg [word-1:0] St13_Muli,St14_Muli,St15_Muli,St16_Muli; reg [word-1:0] St17_Muld,St18_Muld,St19_Muld,St20_Muld; reg [word-1:0] St21_Muld,St22_Muld,St23_Muld,St24_Muld; reg [word-1:0] St17_Muli,St18_Muli,St19_Muli,St20_Muli; reg [word-1:0] St21_Muli,St22_Muli,St23_Muli,St24_Muli; reg [word-1:0] St25_Muld,St26_Muld,St27_Muld,St28_Muld; reg [word-1:0] St29_Muld,St30_Muld,St31_Muld,St32_Muld; reg [word-1:0] St25_Muli,St26_Muli,St27_Muli,St28_Muli; reg [word-1:0] St29_Muli,St30_Muli,St31_Muli,St32_Muli; reg [double-1:0] St1_Ac = 0; reg [double-1:0] St2_Ac,St3_Ac,St4_Ac,St5_Ac,St6_Ac,St7_Ac; reg [double-1:0] St8_Ac,St9_Ac,St10_Ac,St11_Ac,St12_Ac,St13_Ac; reg [double-1:0] St14_Ac,St15_Ac,St16_Ac,St17_Ac,St18_Ac,St19_Ac; reg [double-1:0] St20_Ac,St21_Ac,St22_Ac,St23_Ac,St24_Ac,St25_Ac; reg [double-1:0] St26_Ac,St27_Ac,St28_Ac,St29_Ac,St30_Ac,St31_Ac,St32_Ac; reg [double-1:0] St1_Ac_Bus,St2_Ac_Bus,St3_Ac_Bus; wire [word-1:0] drive_multiplicand; wire [word-1:0] drive_multiplier; assign drive_multiplicand = Multiplicand; assign drive_multiplier = Multiplier; always @ (posedge clk) begin St1_Muld <= drive_multiplicand; St1_Muli <= drive_multiplier; if (St1_Muli[0] == 1) begin St1_Ac [double-1:32] = St1_Ac [double-1:32] + St1_Muld; end else begin St1_Ac [double-1:32] = St1_Ac [double-1:32] + 0; end St1_Ac = St1_Ac >> 1; St2_Muld <= St1_Muld ; St2_Muli <= St1_Muli; St2_Ac = St1_Ac; if (St2_Muli[1] == 1) begin St2_Ac [double-1:32] = St2_Ac [double-1:32] + St2_Muld; end else begin St2_Ac [double-1:32] = St2_Ac [double-1:32] + 0; end St2_Ac = St2_Ac >> 1; St3_Muld <= St2_Muld ; St3_Muli <= St2_Muli; St3_Ac = St2_Ac; if (St3_Muli[2] == 1) begin St3_Ac [double-1:32] = St3_Ac [double-1:32] + St3_Muld; end else begin St3_Ac [double-1:32] = St3_Ac [double-1:32] + 0; end St3_Ac = St3_Ac >> 1; St4_Muld <= St3_Muld ; St4_Muli <= St3_Muli; St4_Ac = St3_Ac; if (St4_Muli[3] == 1) begin St4_Ac [double-1:32] = St4_Ac [double-1:32] + St4_Muld; end else begin St4_Ac [double-1:32] = St4_Ac [double-1:32] + 0; end St4_Ac = St4_Ac >> 1; St5_Muld <= St4_Muld ; St5_Muli <= St4_Muli; St5_Ac = St4_Ac; if (St5_Muli[4] == 1) begin St5_Ac [double-1:32] = St5_Ac [double-1:32] + St5_Muld; end else begin St5_Ac [double-1:32] = St5_Ac [double-1:32] + 0; end St5_Ac = St5_Ac >> 1; St6_Muld <= St5_Muld ; St6_Muli <= St5_Muli; St6_Ac = St5_Ac; if (St6_Muli[5] == 1) begin St6_Ac [double-1:32] = St6_Ac [double-1:32] + St6_Muld; end else begin St6_Ac [double-1:32] = St6_Ac [double-1:32] + 0; end St6_Ac = St6_Ac >> 1; St7_Muld <= St6_Muld ; St7_Muli <= St6_Muli; St7_Ac = St6_Ac; if (St7_Muli[6] == 1) begin St7_Ac [double-1:32] = St7_Ac [double-1:32] + St7_Muld; end else begin St7_Ac [double-1:32] = St7_Ac [double-1:32] + 0; end St7_Ac = St7_Ac >> 1; St8_Muld <= St7_Muld ; St8_Muli <= St7_Muli; St8_Ac = St7_Ac; end // and so on, I dont understand why this way of pipelining is not working Ill post the errors below endmodule
Code:
Errors:
[Synth 8-6014] Unused sequential element St2_Ac_reg was removed.
[Synth 8-3936] Found unconnected internal register 'St7_Muli_reg' and it is trimmed from '32' to '7' bits
[Synth 8-3331] design mul_piped has unconnected port Multiplier[31]
[Synth 8-3332] Sequential element (St1_Ac_reg[63]) is unused and will be removed from module mul_piped.
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