Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Pipelined ADC calibration

Status
Not open for further replies.

airace

Member level 4
Member level 4
Joined
Sep 17, 2002
Messages
69
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Location
Deep in a chip
Activity points
508
pipeline adc calibration

Hi guys...
we were jsut discussing calibration in our team....
can anyone tell me how one calculates the calibration parameters
in a 1.5 bit/stage pipelined ADC

Thx
 

pipelined adc calibration

are you talking about RSD algo.
Amit
 
digital calibration for pipeline adc

hope this will help you..one thesis on pipeline adc.

Amit
 

pipelined adc calibration method

another good one.
 

adc calibration

well..the problem is ...i dont know how to do it.... :oops: :? ...
...tell me one thing.....u hav the following situation :
I need a schematic to contains :-
1. symbols form analog lib
2. functional lib
3. models o/p by model gen
....how do this...and importantly...what is the simulator that u will choose
in simulation setup..

Thx,
 

site:www.edaboard.com pipeline adc calibration

there many kinds of calibration schemes for 1.5b/stage pipelined ADC!
if you want schematics, I am afraid there are not much on web!

some IEEE papers may be helpful:
"Digital_Domain Calibration of Multistep Analog-to-Digital Converters"
"Background Digital Calibration Techniques for Pipelined ADC's"
and so force
 

pipelined calibrated model

I am looking for Digital Calibration technique for pipelined 1.5bits/stage A/D converter .Trip points in A/D are Vref/4 & -Vref/4 and decision points to each stage are 00,01 and 10 respectively based on the region where the Analog residue falls into .MADC is a differential Architecture .

I would like to find Calibration Coefficients for Negative/Positive input & Coefficient for the offset too. I would like to know the following

1)If the differential input has to be sampled with respect to the ground Voltage or +/-Vref/4 ??
2)Do I have to find capacitor mismatch in each stage ??
3)Can I use the same ADC to find the error code ??

thx,
 

adc callibration

Here is transfer function of 1.5bit pipelined A/D.
Vout=2*Vin+D*Vref ->D=1 ,Vin<-Vref/4
->D=0 ,otherwise
->D=-1,Vin>Vref/4
 

calibrated pipeline adc simulink

you dont have to calibrate capacitor mismatch of each stage, just do calibration on MSB of ADC. You can get more details from acticles I have referred upward!
 

rsd 1.5bits/stage algorithm

I think we have to have a backend pipelined ADC for digital calibration or use the same to compute the calibration coefficients .
 

analog calibration pipeline adc

you may search topic "1.5bit | adc" in IEEE Xplore, then you may find related papers. The thesis is too long.
 

capacitor mismatch calibration in pipeline adc

How to build the behavioral model of pipeline ADC by using MATLAB/Simulink?

Is there any reference book or paper?
 

pipelined adc verilog-ams

smap said:
How to build the behavioral model of pipeline ADC by using MATLAB/Simulink?

Is there any reference book or paper?

You can refer to this IEEE paper(2001):

Behavioral model of pipeline ADC by using SIMULINK(R)
 

pipeline adc

Behavioral model of pipeline ADC by using SIMULINK(R).pdf

How can i upload this paper? I tried,but failed.:cry:
 

simulink adc pipeline

holddreams said:
Behavioral model of pipeline ADC by using SIMULINK(R).pdf

How can i upload this paper? I tried,but failed.:cry:

Behavioral model of pipeline ADC by using SIMULINK(R)
Bilhan, E.; Estrada-Gutierrez, P.C.; Valero-Lopez, A.Y.; Maloberti, F.;
Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on
25-27 Feb. 2001 Page(s):147 - 151
 

reason for vref/4 in pipelined adc

I'd like to see your paper
 

different calibration method of pipeline adc

Digital calibration or analog calibration?
 

adc calibration using matlab

Does anybody have the thesis discussing the behavioral model of pipelined ADC by using Verilog-AMS?
 

behavioral model of pipelined adc

I also need info for ADC calibration. As per I know this is the techique to calculate the
error coefficients of 1st few stages with some algorithm.

I also want to know the hardware implementation of this
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top