pipeline adc questions

[userss]

pipeline adc basics

i have some questions about pipeline adc design.

-i want to understand the basics of the digital error correction. how decreasing the interstage gain by 1/2 and bit overlaping corrects the errors caused by the sub-adc.

-why the referans voltages of the sub-adc are +vref/4 and -vref/4. (for 1.5 bit stage.)

-and why is the maximum tolerable error voltage is vref/4. (by digital correction) (error is caused by the sub-adc.)

 

[Usman Hai]

My friend you will have to read some thesis on pipelined adc design. There are many theses which talk very specifically about this like Abo, Cho from berkeley. I am attaching one which I think might help you as well.