Pico second precision up counter

[npsnpsnps]

I would like to know if there is any synchronous up counter which increments at for every 10 ps (At pico second level). Basically a high precision Counter. I tried using 2 D Flip Flops which are made up of 3 input Nand gates. It is working properly for nanosecond precision but not for picosecond precision. Any suggestions if I have to do something with the transistor sizes or I have to change the design itself ?

 

[dick_freebird]

1pS = 1THz and there are no active gain devices that have
that bandwidth, let alone the excess gain*BW that a logic
would need.

Synchronous counters also impose rollover logic that drops
the attainable fClk(max) below what a simple self-toggle
stage could manage. I think you will need to look at a
hybrid counter with a couple of bone-simple, run-hot
ripple counter stages prescaling the input signal to what
sync stages can handle. Those outputs might have to be
re-registered in the end to align with the sync counter's.

Go find the hottest InP foundry flow you can, make a
CML / SCL gate library and see what a ripple and a 4-
stage sync counter can handle. I expect you will not
achieve 1THz, likely not 100GHz (although this seems
to be on the edge of achievable, looking at some
photonic high-bit-rate systems' purported data throw,
though maybe a bit too reliant on parallel lanes and
multilevel signaling).

 

[ThisIsNotSam]

for reference, an inverter in 16nm finfet is about 10ps of delay. certainly can't have a counter work that fast.

 

[npsnpsnps]

Any possibility to achieve 50 GHz speed atleast ?

 

[ThisIsNotSam]

Any possibility to achieve 50 GHz speed atleast ?

ask yourself this question... if it was possible, why wouldn't Intel be selling processors running at that speed? You can't come anywhere near that speed with digital design.

 

[asdf44]

Intel runs at 5ghz and does actual work at that speed.

A ripple counter needs to do literally nothing. Going 10x faster than modern consumer processor clocks speeds with a ripple counter sure seems possible to me.

 

[dick_freebird]

OP asks for a synchronous counter which is a whole lot more
difficult.

I'd bet the 5GHz clock, first hits a PLL*VCO block to make
even higher frequency internal clocks. But what you can do
with transistors on a sing-digit-nm die, and what you can
do with available piece-parts on a PCB, are worlds apart.

 

[npsnpsnps]

I think that is possible. May be not today but sometime in future.

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I think that is possible. May be not today but sometime in future. @ThisIsNotSam

 

[ThisIsNotSam]

Come on now... this is the ASIC digital section. OP asked about synchronous design. Cannot be done today and will not be possible in the foreseeable future, even when we reach 5nm or even below.

Just take a look at the predictions for the newer nodes. 50GHz is not in the realm of possibilities. We will most likely be stuck at the same clock frequencies we have today for a bunch of good reasons.

 

[BradtheRad]

The Josephson Junction has a lot of promise to increase speed of electronic devices, if researchers can find the secret to room temperature superconductivity. Then a wide world of possibilities will open up.

"Josephson-Junction Technology for
Sub-Terahertz Clock Frequency Digital Systems"

http://www.mukhanov.com/uploads/LikharevSemenov-RSFQReview_IEEETAS91.pdf