pic18f4550 FOSC computation confusion

[Primark]

I have the following config for my pic18f4550 running on a 8MHz oscillator
#pragma config FOSC = HSPLL_HS //type of oscillator
#pragma config PLLDIV = 2
#pragma config WDT = OFF //disable watch dog timer
#pragma config LVP = OFF //disable low voltage programming

what I'm wondering is what my FOSC is, supposively this will give me a 48MHz, but when I try to send a data at a baud rate of 57600 using this setting

OpenUSART(USART_TX_INT_OFF &
USART_RX_INT_OFF &
USART_ASYNCH_MODE &
USART_EIGHT_BIT &
USART_CONT_RX &//fosc 48000000, baud is 57600
USART_BRGH_HIGH, 51); //baud rate is equal to SPGRGH SETTING found at page 251 of datasheet

it fails. the recipient of the data is already fixed at a baud rate of 57600 so there should really be no problem. The only thing I'm not certain about is my FOSC so can anyone help me out with this?

 

[john blue]

You need CPUDIV, at PLLDIV, you have 96MHz, CPUDIV is another prescaler. If you didnt change the config in the microcontroller before, then , its ok

 

[Primark]

Thanks for the reply, apparently upon testing it several times I have already proven that it functions at 57600 baud rate so that means I'm definitely getting a 48MHz FOSC. I tested the config via hyperterminal. Thanks for the reply anyways. I also read in the datasheet of pic18f4550 that once you use HSPLL you acquire 48MHz even without configuring the pragma at CPUDIV. CPUDIV seems to be preconfigured at 00 which is CPUDIV = OSC1_PLL2.