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PIC microcontroller debugging- dspic33ch128mp508

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chaminda12001

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Hi ,

I am getting error message when I go to debugging dspic33ch128mp508 curiorsity development board. I inculded the configuration settings at the begining of the programme. error message :

"Target Device Not Ready For Debugging Check Config Bits PGC, PGD Settings".

Is there settings I need to check


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// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)
 
// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)
 
// FOSCSEL
#pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC) Oscillator with postscaler)
#pragma config IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
 
// FOSC
#pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
#pragma config PLLKEN = PLLKEN_ON // PLLKEN (PLLKEN_ON)
#pragma config XTCFG = G3 // XT Config (24-32 MHz crystals)
#pragma config XTBST = ENABLE // XT Boost (Boost the kick-start)
 
// FWDT
#pragma config RWDTPS = PS1048576 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer operates in Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config FWDTEN = ON_SW // Watchdog Timer Enable bit (WDT enabled in hardware)
 
// FICD
#pragma config ICS = PGD3 // ICD Communication Channel Select bits (Communicate on PGC1 and PGD1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
 
// FDMT
#pragma config DMTDIS = OFF // Dead Man Timer Disable bit (Dead Man Timer is Disabled and can be enabled by software)
 
// FS1OSCSEL
#pragma config S1FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC) Oscillator with postscaler)
#pragma config S1IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
 
// FS1OSC
#pragma config S1OSCIOFNC = OFF // Slave OSC2 Pin Function bit (OSC2 is clock output)
#pragma config S1FCKSM = CSDCMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)
#pragma config S1PLLKEN = S1PLLKEN_ON // S1PLLKEN (S1PLLKEN_ON)
 
// FS1WDT
#pragma config S1RWDTPS = PS1048576 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config S1WINDIS = ON // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config S1WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config S1SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1FWDTEN = ON_SW // Watchdog Timer Enable bit (WDT enabled in hardware)
 
// FS1ICD
#pragma config S1ICS = PGD3 // ICD Communication Channel Select bits (Communicate on PGC1 and PGD1)
#pragma config S1ISOLAT = ON // Isolate the Slave core subsystem from the master subsystem during Debug (The slave can operate (in debug mode) even if the SLVEN bit in the MSI is zero.)
#pragma config S1NOBTSWP = OFF // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)

 
Last edited by a moderator:

You did not specify what programmer you are using, and what pins are aavailable to programming connector, anyway if I were you I would investigate this line:

Code:
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
 

Agree with Andre. It looks like you’ve explicitly disabled JTAG.
 

You did not specify what programmer you are using, and what pins are aavailable to programming connector, anyway if I were you I would investigate this line:

Code:
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)

Hi I am using MPLAB IDE 5.10 for debuggging with the dspic33ch128mp508 curiosity developement board
 

Microchip doesn't use JTAG interface for debugging.

I am using MPLAB IDE 5.10
Unlikely, it's 18 years old. I guess you mean MPLAB X IDE 5.10.

Code:
#pragma config ICS = PGD3
You didn't tell which debug adapter you are using, I guess Curiosity On-Board PICkit? If so, it seems to connect to PGD2 according to the schematic rather than PGD3 selected in your configuration. This would cause the reported behavior, programming works but debugging fails.
 

yes it works with PGD2 settings. Thank you very much for help. :-D
 

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