bhargav.scsvmv
Member level 1
What is phase difference between the output of a T Flip flop and and clock signal applied to it,when the input to the flip flop is high.
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there're more than one phase difference.
for the first clock pulse ? I'd say it's unknown from what you provide.Then what would be the phase difference for the first clock pulse and o/p.
Your question is quite confusing but I think as the frequency of output is exact half of the clock when i/p is 1 so it will depend on the logic level of the clock...you didn't mention whether the FF is a rising edge or falling edge triggered one...
I think you are asking the the time between clock rising edge to output toggle. If clock rising edge occurs at t=t_0, output toggles at time t=t_0+t_delay. What is t_delay?
It really depends on the model of TFF you are using. If you are using a discrete IC, check the datasheet, if you are using an FPGA do a post-routing simulation.