Parameterized Generated Case Statement?

[carleethian]

Hi guys, I want to create something like the following, essentially creating a lookup table based on the number of states and max/min that I set outside the generate loop. Can I do this without any problems?

parameter STATES = 4;
parameter MAX = 5;
parameter MIN = 1;

case(r_STATE)
  genvar N;
  generate
    for (N=0; N<STATES; N=N+1)
      begin
        N:
          begin
            r_TICKS <= (MAX - MIN) * 2 / N;
            r_STATE <= r_STATE + 1;
          end
      end
  endgenerate
    default:
      begin
        r_TICKS <= 0;
        r_ACCL_STATE <= 0;
      end
endcase

I basically want to create a lookup table that I'm going to need to iterate on and don't want to have to type it in each time. Therefore I'd prefer to have my lookup table be generated pre-processor each time. Only inputs would be essentially be lookup table size and slope of "r_TICKS".

Thanks.

 

[carleethian]

So... I guess there's nothing that exists in Verilog to generate a bunch of statements in the pre-compiler?

Is it possible to put a generate or for loop inside an always block at all?

 

[dave_59]

Does this need to be synthesizable?

You can't put a generate block in the middle of procedural code, but you can use it to generate multiple initial/always blocks.

 

[carleethian]

Yes, it needs to be synthesizable. I'm essentially creating a lookup table. I've decided that using an array and initializing that array using directives or something like that would be optimal... I essentially want to create an array and then initialize each value in the array by using it's array index as an input to an equation. i.e.:

reg [7:0] array [0:31];

for(i = 0; i < 32; i = i+1)
  array[i] = 4000 / (i + 1);

Or something like that, I just need it to be synthesizable and the values in the array would be generated synthesis.