output is different than simulation

[david753]

I use Modelsim to simulate timing and function simulation.
The result is right.
But, when I download it to FPGA, the function is wrong.

What wrong is it?
How to debug it?

 

[Sathish]

there are lot of difference between the model sim output and the FPGA implementation output. to say where you made the mistake just post the program or send me a mail. sathishkumarsha@yahoo.com

 

[Big Boy]

You probably have non-synthesizable code, or using dangerous directives.

For example, bad use of parallel case and full case in Verilog:

http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf

Or

http://soccentral.com/goto.asp?EntryID=1124

 

[shankarmit]

ya sure it will be wrong until you backannotate it..

did you synthesize it using leonard spectrum for that fpga and get sdf file and backannotate it..


check the warning given by xilinx while synthsize and translating ...
for example it will remove the initial values.. if you use initial values for some logic.. it goes wrong...


Regards
Shankar
Tallika

 

[Jackwang]

I meet with the same problem.
I design a digital filter, which simualtion is correct, but after I download it into FPGA, it don't work correctly. Its output is correct partly, and the phase of some output point appears overturn.
I don't understand why?

 

[tkbits]

If synthesis is producing warnings about incomplete sensitivity lists, then your simulation model is wrong. To make the simulation match what synthesis creates, you will need to add the missing items of each incomplete sensitivity list.

That's one possibility.

 

[Manny_Calavera]

Jackwang,

Apparently, your filter is overflowing in some points which are not covered by your testbench. Check out your saturation logic and accumulator width. In my opinion, the best testbench for filters in general is a ramp function that covers the whole dynamic range of your quantization levels as it’ll show exactly what is your filter made from hehe.

Cheers.