Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Output buffer design - suggestions

Status
Not open for further replies.

whirl7wind77

Junior Member level 2
Joined
Dec 16, 2013
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
130
Can anyone suggest the type of buffer i should use to connect the output to transmission line with Zo 50 ohms through a bypass capacitor.
 

3 dB frequency is around 8 GHz.

[This buffer exists between the output of the amplifier and the load which is a high bypass capacitor followed by a transmission line.]
 
Last edited:

you can try CML driver with 50ohm resistor loading. the current is dependent by how much signal swing you want to get.
it is strange to me that typical the high pass capacitor is put at the end out transmission line. why in your case it is at the beginning of line?
 

I forgot to mention that the signal is not digital. Its analog. So I think I cannot use CML driver.
 

What is your power consumption constraint and output dynamic range relative to your power supply.
 

The output resistance of amplifier is 3K. This output is to be connected to load 50 ohms followed by a bypass capacitor through BUFFER . This buffer should not decrease Bandwidth and Gain .

[ Supply Voltage is 1.2 V, the output swing is 0.15V and there is no much constraint on power consumption. ]
Please suggest some ideas.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top