out put of Tri- State component (TBUF) to a Register in FPGA.

[Mirzaaur]

Dear All,
I need advice about using tri-state (TBUF) compnent in FPGA design.

question:-

if output of tri-state is connected to input of a register then what will be the logic value stored in register while tri-state is in high impedance state?

best regards,

mirza

 

[FvM]

Unknown (in simulation) or don't care respectively unpredictable (in a real design). Internal tri-state nodes can be used in HDL code, but they aren't synthesizable, the design compiler is usually translating it to multiplexers. Their logic output can be only '0' or '1', but not 'Z'.

 

[permute]

It actually depends on your device. There are Xilinx devices that had internal tri-states. Mostly old devices, but it looks like there might still be a CPLD that allows it. Its possible other FPGA/CPLD devices exist with this feature.

The newer FPGAs don't have this feature.

As for the value of the net, I'm not sure. This document seems to suggest either unknown or 1.
**broken link removed**
**broken link removed**

 

[FvM]

You are right, the usage of BUFT internal tri-state buffers and bidirectional routing busses is shown e.g. in the Spartan-II functional description. It can be expected however, that the logic level of the undriven bus (all BUFT tri-stated) is unpredictable similar to an external bus. Otherwise, the routing bus would need pull-up or pull-down resistors to implement a defined state. But power efficiency considerations are effectively forbidding it.