optimizing the dead zone in the PFD/CP

[mmohsen]

Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang:” A Difference detector for Low Jitter PLL.”, Electronics Circuits and Systems, 2001.ICECS 2001.The 8th IEEE International Conference on, Volume: 1, 2001, pp 43-46 vol.1.

could you upload this paper please as i didnot find it on the web or tell me from where i could get it ,

thanks in advance,..

 

[mmohsen]

thanks alot for this paper ,
i am asking if you have more resources about this issue would you upload them ??!!

thanks in advance

 

[amarnath]

i will need to searcvh through my papers,will surely do it.

regards
amarnath

 

[xusoso]

The basic configuration of the phase detector includes two D-type
flip-flops with feedback to restore both to the initial state
after both have been clocked. A delay in the feedback path
establishes the minimum time that either flip-flop is in the
clocked state, thus establishing a minimum time that current
sources are switched on.

The delay is selected to insure that both current sources are
first turned fully on before they are turned off. This feature is
necessary to eliminate dead-band whereby the phase detector does
not respond properly to small phase errors (or time differences)
between the two input signals to the phase detector.

Thus, adding delay to the feedback path can solve the deadband
problem.

 

[hanjiemy]

1. need enough delay time for reset signal of PFD.
2. minimize the delay time of UP/DN.
3. minimize the setup time of source/sink current.
4. minimize the mismatch/leakage of source/sink.
5. delay time must be minimzed and large pulse width will increase spur.

 

[Alles Gute]

To avoid Dead Zone we need long reset time;
To decrease Charge Pump current mismatch effect we need to decrease reset time.

So, how to get the "Optimal" point? How can I know how much is the minimum reset time (in order to avoid DZ)?

 

[rfsystem]

Did you have a sigma-delta driven PLL?

 

[spec07]

The basic configuration of the phase detector includes two D-type
flip-flops with feedback to restore both to the initial state
after both have been clocked. A delay in the feedback path
establishes the minimum time that either flip-flop is in the
clocked state, thus establishing a minimum time that current
sources are switched on.

The delay is selected to insure that both current sources are
first turned fully on before they are turned off. This feature is
necessary to eliminate dead-band whereby the phase detector does
not respond properly to small phase errors (or time differences)
between the two input signals to the phase detector.

Thus, adding delay to the feedback path can solve the deadband
problem.

Any diagrams on where to placed the delay to the feedback path as mentioned?

Will this delay help in reducing the delay between the reference clock and input clock of and DLL?

 

[wlo333]

My PLL locks with a constant small phase difference between the ref. and the feedback clock. So the up pulse width is 200ps longer than the down pulse. This cause freq. jitter at the output.
How do I fix it to lower the freq. jitter?

wlo333