opamp osciltions problem which didnt show on LTSPICE

[yefj]

Hello , i have designed with a big help from this forum a driver.
at first glanse it amplified great the signal how ever when i probed R1 resistor as shown below on my lab scope with DC input , i saw oscilations.
Now when i did step responce of the circuilt as shown below i see the oscilations.
I also know from analog design course that i can try and see the AC responce.
LT1028 is -1 stable ,how does it influence the connection between the stages so i will not get oscilations.
What could cause instability in such configuration?
Thanks.

https://www.analog.com/media/en/technical-documentation/data-sheets/1028fd.pdf

 

[FvM]

Output stage has additional loop gain created by transistors and phase lag due to inductor, so it's not necessarily stable.

 

[KlausST]

Hi,

So the simulation worked (schematic)
The real circuit oscillates

but to find the issue you only showed us the (working) schematic.

It´s like: you have two cars, one is green the other red. The green one does not start ... so you give the red one to the garage for finding the problem.
--> What I want to say: If you encounter a problem with your real circuit, then show us your real circuit.

We don´t see the power supply, we don´t see that GND wiring. Both are "ideal" in a schematic .. this means "not realistic".

**********************
You also say the LT1028 is stable with -1
But U1 has a positive gain.

**********************

Klaus

 

[D.A.(Tony)Stewart]

I don't understand why you screw up this design with under-compensated Op Amps

 

[FvM]

Phase margin in simulated loop gain is rather small. But we can't be sure if real loop gain exactly matches simulation due to model inaccuracies, different load impedance, possible parasitic circuit effects like crosstalk to preamplifier. Additional compensation may be useful.

What's required driver bandwidth?

 

[danadakk]

Was your scope probe set to x1 or x10 ?

Post picture of your prototype ......

What are you using for bypass caps on OpAmp supply pins ?

I get ~ 35 degrees of phase margin when doing bode sim, and following transient
response :

Regards, Dana.

 

[D.A.(Tony)Stewart]

The LT1028 was designed to maximize BW open loop at the expense of phase margin and has not been optimized for phase margin. There are external compensation pins not shown in my model or yours , yet they were ignored in your design.


I 'd like to remind everyone to design by "MUST HAVE" specs , then do whatever it takes to achieve your goals. The "NICE TO HAVE " specs are just bonuses.

I assumed you wanted to minimize overshoot to 2% and suppress resonances that cause sidebands in your YIG. But you need to specify values for EVERYTHING you anticipate as a fault.

Take # 21. Since you are not doing what I ask, you will have to observe or guess what changes I made to improve your results at 40% duty cycle for each stage normalized by gain changes.

Even this may not reflect your physical cable impedance and unknown lengths.

By your asking intelligent questions and searching for answers, you will learn, but a good design book is needed and better questions.

https://ia902808.us.archive.org/22/items/bobpeaselabnotespart8/Bob%20Pease%20Lab%20Notes%20Part%208.pdf

https://ia803102.us.archive.org/10/items/Bob_Pease_Lab_Notes_Part_9/Bob_Pease_Lab_Notes_Part_9.pdf

You can find the earlier chapters there.

 

[yefj]

Hello Mr. Stewart, yes you are absolutely right .There is a over-comp leg on the LT1028 which is not present in the simulation.
You even predicted the stability issue shown in the link below,so i am trying to follow my best with your advices.
So if i go back from where i started in the schematics shown below, could you please recommend me steps i should do to stop these oscillations?
Thanks.

https://www.analog.com/media/en/technical-documentation/data-sheets/1028fd.pdf

driver compression logic

Hello, I have the following circuit where the heart is the BJT.when i put the resistor to be 50Ohms i get a good sine current on the inductor L1 shown below. But when i put 25 ohms i get compression . In the compressed version i see that the current going threw the inductor is much higher and...

www.edaboard.com

 

[D.A.(Tony)Stewart]

No.

Start with full design specs for good performance and errors like overshoot, and component availability, lead time, project time / budget limit.

For example, I could better performance with a different IC, but you insisted no change for no good reason. For example is this for an undergrad thesis or a private company. Do you have time to re-spin the PCB or not. Is this for qty=1 or future volume=?

 

[danadakk]

The LT1028 was designed to maximize BW open loop at the expense of phase margin and has not been optimized for phase margin.

From datasheet "The LT®1028(gain of –1 stable)/LT1128(gain of +1 stable)"

Then we have :

So phase margin definitely a cliff hanger, but then Cload curve they snuck in
some G rolloff in test circuit.

Then we have this (thanks ADI for a "guess what to do with this pin" approach) :

LT1028 or LT1128 - LTspice models with Compensation Pin? - Q&A - Operational Amplifiers - EngineerZone

Are there any LTspice models for the LT1028 or LT1128 that have the compensation pin? Or is there any other way to simulate this? Maybe there is a parameter that

ez.analog.com

Regards, Dana.

 

[D.A.(Tony)Stewart]

Then we have :

View attachment 187663

So phase margin definitely a cliff hanger, but then Cload curve they snuck in
some G rolloff in test circuit.

Then we have this (thanks ADI for a "guess what to do with this pin" approach) :

LT1028 or LT1128 - LTspice models with Compensation Pin? - Q&A - Operational Amplifiers - EngineerZone

Are there any LTspice models for the LT1028 or LT1128 that have the compensation pin? Or is there any other way to simulate this? Maybe there is a parameter that

ez.analog.com

Regards, Dana.

The non-inverting input is better if the source impedance is not 0 and will be better to reduce the negative feedback overshoot. Thus the phase margin is improved by increasing risetime (slightly) for any Rs source.

Clues

 

[yefj]

Hello , my specs are 20mA threw the could so my YIG will move 12MHZ from end to end.
My components are not burning because i lowered the DC supply so there is no problem.
the only spec is i put DC voltage in the input and i get a steady DC (with no oscillations on the output).
My voltage input is from 0 to 10mV pk-pk and it need to ne 20mA.

reading the data sheet they say i show connect the capacitor from this leg 5 to the output.

I can try in real life to input a step response to my circuit and see the overshoot on the output.( to see phase marging issue)
So by the phot below i need to connect a capacitor between opamp output to ground and see how it handles overshoot?( and its an alternative to use leg 5 OVERCOMP)
If its this a good idea, i will start by putting 90pF?
Thanks.

 

[danadakk]

Compensation principles :

Generally speaking adding Cload aggravate phase margin.

https://www.ti.com/lit/an/slva662/slva662.pdf

https://www.ti.com/lit/an/sloa020a/sloa020a.pdf?ts=1704784632455&ref_url=https%253A%252F%252Fcn.bing.com%252F

Regards, Dana.

 

[D.A.(Tony)Stewart]

That is not an adequate design spec for your circuit. A design spec is a table of parameters, with tolerances {min:max or Nominal: +/-%} and test conditions (assumptions) listed for each like a datasheet. You get better at this with practice.

It should list all the critical requirements found in component datasheets then you choose the components that meet it and include tolerances of resistors and all passives required including source , load , cable impedance+ lengths, supply specs etc.

If you were designing an Op Amp, like the LT1080, I would expect a design spec to include the following. But your requirements are much relaxed so this Op Amp is "overkill" for both cost and yet under-compensated for step response. Ideally you want critical-damping. Do you know how that is defined? You must also define your environmental specs like a "benign" lab using 25'C or outdoors with full temperature range shown below or something in between.

 

[danadakk]

Generally speaking adding Cload aggravates phase margin because the Zout
of an OpAmp is inductive in nature, rises as gain is lost as frequency rises.

You can compute this by doing a LaPlace analysis of Zout for 1 and 2 pole OpAmps.

Regards, Dana.

 

[D.A.(Tony)Stewart]

If you do not have LTspice, install it and learn how to use it then open the Zip and open the .ASC file or extract it to your folder, Documents\LTspiceXVII\examples then open the *.asc schematic file and run it then add probe points. Use Labels, Measure current inside components or Voltages outside with pointer on schematic. Add gain equations to Edit plots to compare easily each stage. Modify current with R value changes. Simulations can be done in 5 minutes with practice. trial and error by PCB changes can take weeks when you do it the way you have.

--- Updated Jan 9, 2024 ---

I never had these tools in my career, so I just learned how to use it in the last couple months.
But you can use LTspice for WIn10 or XVII for Win 7 which I greatly prefer.

LTspice Simulator | Analog Devices

LTspice® is a high performance SPICE III simulator, schematic capture and waveform viewer with enhancements and models for easing the simulation of switching regulators. Learn more about the benefits of this simulator software.

www.analog.com

But experts will prefer MATLAB or use Python or even better free MICROCAP 12 which I have not mastered yet, or Simetrix which @dana uses or many many other tools. Your career will depend on you mastering some of these tools and more.

--- Updated Jan 9, 2024 ---

The design specs are Oscillating here. (silent c)

 

[Audioguru]

Your schematic had many jogs in its wiring (caused by Multisim?) and it had its parts very far apart making it huge.
I fixed it:

 

[D.A.(Tony)Stewart]

Your schematic had many jogs in its wiring (caused by Multisim?) and it had its parts very far apart making it huge.
I fixed it:

Thanks AG but I did it intentionally to show the logic of avoiding a large feedback loop for whatever reasons like avoiding parasitic coupling to the positive feedback Vin+ in the layout.

Then corrected the distortion from -ve feedback by using Vin+ with gain adjusted for 50 mA , which is now apparently 20 mA. from 50 and 100 mA before.,

 

[yefj]

Hello Mr. stewart ,your circuit looks quite different from the structure i have made.
When i ran the simulation i get this current threw a coil far from the expected rectangular shape.
and i use 7.5 Volts not 15 because my components were butning with 15V.

I need to think of a method on how to investigate stability in real life and see how exactly its getting better of worse.
Could you please recommend me how with lab equi[ment i can see if my stability get better or not?
Thanks.

--- Updated Jan 10, 2024 ---

UPDATE:



My circuit has a very simple goard i put DC voltage of 10mV and i get 20mA on the inductor.
pure DC signal.
My goal is to learn how to investigate stability issues of a circuit i have built
I can do LTSPICE sinulations to learn how to tune the circuit into stability.
There could be many issues, maybe i have noisy power supply .
Maybe i have bad decoupling circuit.i need to learn how to investigate in real life.

suppose i have oscilations on my scope instead of DC, how can i know the phase margin situation from it?
looking at the AC responce i cant see anywhere a point where i have 0dB and 180 phase(barkausen condition)

Thanks.

 

[KlausST]

Hi,

When i ran the simulation i get this current threw a coil far from the expected rectangular shape.

the problem is that you ignore how an inductance works.

dI = V/L

it says: if you want a high rise rate in current (like the edge in a square wave) --> you need to apply a high voltage.

But for the advantage of low power dissipation you reduced the voltage. Now you miss the voltage to achieve a rectangular current waveform.

I can´t remember that you specified a rectangular waveform before. Maybe you did. If you did not: don´t complain!

Klaus