opamp design - bias current of 10uA Vsupply=3.3v.

[ramya19]

opamp design

I am trying to design an opamp. I have supplied a bias current of 10uA Vsupply=3.3v. 10uA is flowing through the diffpair branches (current mirror as well as input pair) The problem is the input pair transistors are in cutoff and all others are in saturation. Please suggest me what to do.
Thanks in advance.

 

[ieropsaltic]

Re: opamp design

Hello,

What gate voltage did you use to bias the differntial pair? You should use a gate voltage that would ensure that the diff pair devices are ON and would give enough headroom for the current source.

If you'd kindly upload the testbench and the schematic, it'd be easier for us to debug the problem.

Thank you and good luck.

 

[coolstuff07]

Re: opamp design

Hi,

If you are designing standard 5 transistor differential amplifier then your input voltage of the differential pair should min one Vdast of tail current source + vgs voltage of the input transistors (i.e., Vth + 2 * Vdsat).

Bye.