kaushikrvs
Member level 5
How does reducing number of clock cycles per instruction might increase the period of clock cycle? Can anyone please provide a clarity for this tradeoff?
I found this while reading the book Computer organization and design, RISC V edition, In the section 1.6 perfomance
I found this while reading the book Computer organization and design, RISC V edition, In the section 1.6 perfomance