Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NTAPS and PTAPS and its necessary?

Status
Not open for further replies.
Every MOSFET carries a BJT inside it. "Taps" are the closest-in
access point for those devices' base resistance. Parasitic SCR
structures which sustain latchup are composed of two BJTs,
at lease one of them needs to be so strongly base-shunted
that it cannot be kept turned on by the current that the (any
local, other) complementary one can throw. This latter, is a
very variable thing and your "tap" distance rules have to
enforce the worst case (unless you want to perform and
believe in, an awfully elaborate and exhaustive TCAD analysis
and get your boss and your customer to buy off on that basis).

If you want to understand, construct yourself an SCR using
foundry models for parasitic BJTs (that's a joke, son) and then
explore how base shunting increases minimum holding current.
Getting to the worst case sensitivity though, that can only
happen post-layout, which is a bit late and effort-consuming
and by that point you really wanted the risk, gone. Start with
taking the rules at face value until you can do better.
 

I think that the pictures on wikipedia are very clear: https://en.wikipedia.org/wiki/Latchup
In order to make sure that the parasitic PNP/NPN BJT's are off, the voltage drop over the PN junction (the VBE of the BJT) must be <0.6V). This voltage drop is the resistance between the bulk and substrate multiplied by the current throug it (Ohm law...). Using the NTAPS/PTAPS, this resistance is minimized and the latchup risk is gone.

Taps connect the substrate or well to VDD/GND. When you surround e.g. your circuit with P-taps, your substrate/well has a low-ohmic connection to Ground/VDD. This keeps noise currents through the substrate away from your circuit.

So taps prevents against latchup and are used to minimize substrate noise.
 
Last edited:

Hi hope dont mind ask a question here. Can some one tell me can i design like the attach file? The VSS1 is didnt tie to any taps.
 

Attachments

  • 2014-09-05 17.18.40.png
    2014-09-05 17.18.40.png
    164.9 KB · Views: 63

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top