not getting Clock of 25 MHZ for Ethernet in Spatran 3E starter ki

[moonnightingale]

I am using Spatran 3E. I have made a code to capture the data packets on ethernet port. I am using the clock of ethernet port which is 25 MHZ but i am not getting the result. When i checked the clock output on Chipscope, it have a constant high level of 1. then I checked the UCF and i have used the exact same statement of manual

NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;

When i check the Board clock of 50 MHZ FPGA, i get the clock on Chipscope whcih is perfect.
Why my ethernet clock of 25 MHZ is not working. How can i cross check, is there any probability that my crystal is Unserviceable. Kindly tell me some technique to check that my crystal is generating clock.

Secondly if i use clock of 50 MHZ with ethernet,, what will be the effects.

Why we are having special clock for ethernet. Why cannt it use Board Clock

 

[Scrts]

You have to sync FPGA to PHY clock. If there is possible RMII mode, then 50MHz clk is OK. Anyway, check if the signal comes to the PHY itself with an oscilloscope, also You can do simple logics: Input_pin_from_PHY -> internal_signal -> output_pin and then check with oscilloscope. Also You have to do a sync with FPGA, then use two times FF sync.

 

[moonnightingale]

You have to sync FPGA to PHY clock. If there is possible RMII mode, then 50MHz clk is OK. Anyway, check if the signal comes to the PHY itself with an oscilloscope, also You can do simple logics: Input_pin_from_PHY -> internal_signal -> output_pin and then check with oscilloscope. Also You have to do a sync with FPGA, then use two times FF sync.

Is there any method which will work without oscilloscope

i mean software method

 

[Scrts]

If chipscope doesn't show any activity on the input pin, then I believe there are no other methods.

 

[permute]

Make sure you do a bit of research on MII/RMII/SMII. The board might have some jumpers to select between these. Otherwise, you have to use the PHY MDIO/MDC lines to configure the phy. You actually might need to do that anyway. I'm not sure if your PHY requires any special commands. There is a reset command, as well as a reset pin. IIRC, there are also clock enable lines. for RMII, there may also be delay settings (This is an option for RGMII on some gigabit PHY's). The latter might not be needed if the PCB has the traces laid out for RMII.

Overall, I'd start with the reset, MDIO, MDC interface first.

 

[Scrts]

Yep, that would be a good start. Btw, is it possible to do a one-time-configuration-send without using softcpu? Otherwise the configuration will be sent continuously to the PHY.

 

[permute]

I suspect that depends on the PHY. the 88E1111 for example has a lot of multi-level config pins that are sampled on reset to configure most things. There might be jumpers on the PCB to select between MII/RMII/SMII, assuming all are supported. the mdio interface is still a very useful bus for debugging, as it gives link status and control features.

The OP can check to see if the PHY is able to link. The PHY should be able to unless it is held in reset.

as to the OP, just get used to having many slightly different clocks.