No idea how to debug this problem in order to solve it.

[kostbill]

Hello.

If something works in the simulation, is it possible not to work in real life?

I have written a module in VHDL that works fine with my testbench but I have problems when I am running and debugging it.

It is an I2S module, integrated into the Xilinx PLB wrapper. When I send data from an external IC, I always see the correct data, but not in the correct time. For example, sometimes I don't get any data, or the data I am getting are not the data that I am supposed to get at that time. But it's data that I give from my external IC (they are values of a 32 kHz sampled sine). So, I know they are correct because I put them there.

It is like the FIFO registers in my PLB wrapper are not working correct, but I cannot imagine what I have done wrong. I tried every different version and some tutorials, and everytime I have the same problems.

The thing is, I don't know what causes the problem. Is it my module? Is it that I am handling the FIFOs wrong in my SDK? Is it the debugger?

Can anyone suggests a debugging guideline procedure for a problem like that? An idea or something?

Thanks a lot,
Bill.

 

[lostinxlation]

There are many cases that work with simulation, but don't work in the real world.

For example, you have an async fifo and you didn't make the pointer gray coded when it crosses the clock boundary. In simulation it works since the clock is ideal and there is no clock skews, but the silicon has clock skew which could make it fail to capture the all the bit change in the pointer at the same time and the pointer goes crazy.
it's just an example, but there are many such cases.

The first thing I suspect is clock especially when built-in function doesn't work and FIFO is involved with it. Check if the clock speed is right.

if you can hook up the logic analyzer to FPGA outputs, modify the design to output some of the internal nodes and monitor the signals to see if those nodes are behaving as expected.

 

[kostbill]

As a matter of fact, the i2s module is asynchronous from the PLB wrapper. But, if this was the problem, then wouldn't also my data be corrupted?
Also, I am talking to the FIFOs, only through the PLB wrapper, which are not asynchronous. The problem could be caused from the communication of the asynchronous i2s module and the PLB wrapper but I cannot see how.

Do you mind if I post my VHDL code here? It is not long.

Thanks.

 

[lostinxlation]

Sorry, I can't see the big picture of your system.. Please clarify the detail what blocks are involved, how they are connected, where you are seeing the correct data and incorrect data.. etc.. That helps.

The best way to debug on FPGA is picking up a couple of key signals inside the design, modifying the design in a way to pull those signals out on the external pins and recompile it onto FPGA. Then monitor those pins by logic analyzer and see how the internal logic is behaving. You may need to do this a couple of times with different nodes, if there are many nodes to monitor and pins on FPGA is limited. It takes time but it's the most solid way to narrow down the problem.

 

[kostbill]

I will see some signals, although I have no idea what these should be.

This is my system.

An i2s module, it is a slave so it takes it's clock from the external device, which also gives the data.
The clock input is a clock input pin in the FPGA and I have also declare that in the ucf.
It takes the serial in data and outputs the data as 16 bit signed integers. It is asynchronous from the rest of the system.
The only clock in this module is the i2s clock as I stated above.

entity i2score is

generic(width : integer := 16);
port(
LRCIN : in std_logic; --Left/Right indicator clock
BCLK : in std_logic; --Bit clock
DIN : in std_logic; --Data Input
RESET : in std_logic; --Asynchronous Reset (Active High)
DATA_L : out std_logic_vector(width-1 downto 0);
DATA_R : out std_logic_vector(width-1 downto 0);
STROBE : out std_logic; --Rising edge means data is ready
STROBE_LR : out std_logic
);
end i2score;



A wrapper for the i2s module. It takes the data, it synchronizes with the PLB clock and feed the data to the PLB FIFOs.
Note that the two data outputs (data_l and data_r, the strobe and the strobe_lr are not synchronized with the PLB clock
but with the BCLK of the external device. I have some VHDL code to solve these problems (I wonder if there is a mistake there).

An external AVR to simulate the i2s protocol. It outputs a 32 kHz sampled sine of 1 kHz. So, I know the values that are to be transmitted.
Each time I push a button, two values are outputed. Right channel and left channel. There is no problem with bounce.

My main program in SDK goes like this, I check in a while(1) statement the status register of the FIFO, to see if I have a new word written there.
If yes, I read from the FIFO the first word.

Now, in different versions of my program, I get slightly different mistakes, the program I am working on now, has this problem:
When I push the button to transmit a value, I get nothing from the FIFOs, when I push again, I read that there is a value in my FIFOs, but not the values I am expecting.
The values are perfectly valid but not for the time I pushed the button. I was expecting them later or sooner. I can really not find any patterns in this behavior.
I wish I could see that there is one value missing in a standard place but no.

Any ideas?

---------- Post added at 07:00 ---------- Previous post was at 06:19 ----------

I find what is wrong, but I don't know how to fix it.

The FIFOs are supposed to get two values, one after the other, with the push of the button in the external board.

It notifies me that I have data, I read the data and it does not notify me again for the second data. Still, when I read, I read the second data and then it does not notify me again that I have other data.

It seems to me, that somehow that data in the FIFO are overwritten from the next data. Is it possible?
Do you have any idea what can be wrong?

Thanks again.