Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NMI (Non-maskable Interrupts) nets definition and how it works on server

Status
Not open for further replies.

Enshuo

Junior Member level 2
Junior Member level 2
Joined
Jun 28, 2020
Messages
23
Helped
0
Reputation
0
Reaction score
1
Trophy points
3
Activity points
156
Hi experts,
I study an NMI (Non-maskable Interrupts) function, but I don't know how it works detailedly. Please advise me on how and what the nets BMC_CPU0_NMI_CTL_N (BMC to CPU)、CPU0_BMC_NMI_ACTIVE_N (CPU to BMC) mean below.

I assume a server system crashes. Then, press NMI button. BMC sends a control signal to CPU, so it's called CTL? CPU sends a command to BMC to save a memory dump, so it's called ACTIVE (Intel calls EVENT?)? Is it right?
 

Hi,

Please be so kind and give some hint about what controller you talk about.
There are many thousands...

And please additionally gove some context.

Klaus
 

Hi,

Please be so kind and give some hint about what controller you talk about.
There are many thousands...

And please additionally gove some context.

Klaus
Thanks for your reply. Found an example. It's from PCH (C62X series) to BMC (AST2500). Please advise the function of ACTIVE or EVENT.
1598324267541.png
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top