Newbie about initial state of FPGA

[vitiluck]

Whenever a programmed FPGA is powered up.

What initial state is ?

That's when a state machine in the design. when power up, it is not sure which state it is in.

so if a idle state is implemented, a good state machine designed must ensure the FPGA is in IDLE after finite clocks.

But if Bus COmmand issue when FPGA is in unknown state, the first response would be wrong.

Is my understanding right?

 

[vishwa]

Hi

To work the FPGA as you designed, for all the signals, you must assign initial values. Otherwise, the FPGA assigns 'zero' as the default value to all signals whenever it is powered up.


Regards,
Vishwa

 

[bpu]

FPGA doesn't assigns 'zero' as a default value.
Your synthesis tool assign the default values of all the registers in FPGA, it can be non zero.

 

[BuBEE]

How I can set default in synthesis tool , I want set to '1'

 

[vishwa]

Hi bpu

Once the system is designed and the core is downloaded on to the FPGA board (into non-volatile memory). then we don't use any sysnthesis tools in real time operation. Of course, the synthesis tool make the FPGA design to have the signals with 'zero' initial values.

Regards,
Vishwa

Added after 7 minutes:

Hi BuBEE

You can not set the signals using synthesis tool. You have to assign the values to your signals in your VHDL program.


Regards,
Vishwa

 

[vitiluck]

the FPGA assigns 'zero' as the default value to all signals whenever it is powered up.

if I write a code like this

reg na, a;
assign na = ~a;

na and a can't be set initially both to 0 or 1.

 

[echo47]

In most FPGAs, you can initialize registers in your HDL, like this counter in Verilog:

module top (clk, count);
  input clk;
  output reg [15:0] count = 12345;

  always @ (posedge clk)
    count <= count + 1;
endmodule

If you don't specify an initial value, the place-and-route tools normally choose zero.

For Xilinx FPGAs, that is described in the XST User Guide, section Verilog Language Support, subsection Behavioral Verilog Features. VHDL is roughly equivalent.