zengbo
Newbie level 6
Hi, all,
I meet a prolbem when I use the verilog-XL.
It generates a netlist from a schematic. And the netlist has some problems.
There is a port name " BusD<6,4,2,0>", so the netlist generated by verilog-XL is as follow:
module BlockD(control, wr, si, {BusD[6], BusD[4], BusD[2], BusD[0]}, ad, sel, .....);
And "BusD<6,4,2,0>" is not in the input/output/inout definitions part.
I don't know how it happened.
Any body knows?
I meet a prolbem when I use the verilog-XL.
It generates a netlist from a schematic. And the netlist has some problems.
There is a port name " BusD<6,4,2,0>", so the netlist generated by verilog-XL is as follow:
module BlockD(control, wr, si, {BusD[6], BusD[4], BusD[2], BusD[0]}, ad, sel, .....);
And "BusD<6,4,2,0>" is not in the input/output/inout definitions part.
I don't know how it happened.
Any body knows?