r1caw ex ua6bqg
Member level 2
Hi all!
I am a student studying digital design in the university.
I have a question about Synopsys IC Compiler commands which can help reduce negative setup slack in the clock gate path. I know that this situation because of late arrival of launch clock (i.e. clock skew) in comparison with capture (for clock gate) - launch clock delay is more than capture clock delays.
So, how I can solve this problem? May be there is some commands for ICC compiler?
Thank you!
I am a student studying digital design in the university.
I have a question about Synopsys IC Compiler commands which can help reduce negative setup slack in the clock gate path. I know that this situation because of late arrival of launch clock (i.e. clock skew) in comparison with capture (for clock gate) - launch clock delay is more than capture clock delays.
So, how I can solve this problem? May be there is some commands for ICC compiler?
Thank you!