Need suggestion for FPGA to FPGA interface

[Mkanimozhi]

Hi Experts,
I need to design alogic which interface between the two FPGA's , My first FPGA is having PCI interface and my second FPGA is having user application, which is the best way to interface between these two, the interface design should be compactiable with pci protocol.
Am thinking to use DMA interface between these two ,any other good design techniques are recommended.

Thanks and Regards,
Kanimozhi.M

 

[Sink0]

I think most simple solutions would be a local 32 bits bidirectional parallel communication.... you would have as a result something like a PCI 9030.... Ifyou have tons of spare pins you could imlement wishbone.

Cya

 

[YUV]

I completely agree with Sink0
If you use PCI as an interface between FPGA, you will have to implement PCI controller in the second FPGA chip. It will take extra FPGA resources.
Local 32 bits bidirectional parallel bus looks as much more attractive (and simplier) solution.

 

[Mkanimozhi]

Dear Friends,
My first FPGA have PCI interface with my system and in the second FPGA i have my applications, so i need to transfer the data between the First FPGA which is having PCI interface to the System and the Second FPGA having my application.


Regards,
Kanimozhi.M

 

[farhada]

It all depends on how you want to connect the 2. If you have problem with the PCB, you may consider a simple high speed bidirectional link between the 2 FPGAs. Or if you are OK with having lots of signals going between the 2 FPGAs then you can use a parallel connection such as OCP ( Follow this link) which is an industrial standard (it is mostly for inter IP communication, but it can be implemented between 2 FPGAs as well).

You can also find an interesting article describing the concept of inter-FPGA communication **broken link removed**

But, it all depends on what you want to achieve, a simple SPI interface can be sufficient for many applications if your speed is not to high, but if you want to get the full speed of the PCI between the 2 FPGAs, then you have to either create a protocol yourself or use one that works for you the best.

Cheers,
/Farhad Abdolian

 

[YUV]

Dear Friends,
My first FPGA have PCI interface with my system and in the second FPGA i have my applications, so i need to transfer the data between the First FPGA which is having PCI interface to the System and the Second FPGA having my application.


Regards,
Kanimozhi.M

I had PCIe project several years ago. I can't disclose details but in general architecture was like shown in the picture. The 1st FPGA worked as a local bus controller and provided interfaces to synchronous memory in the same board and another FPGA which was located in a separate board. Actually, these interfaces (LB1, LB2) were absolutely same as the local bus of PEX8311. The same set of signals and same algorithm have simplified data exchange between all these devices.
Writing access was not a problem at all. Reading access has required a little management of acknowledge signals and delays of data.
As soon as an architecture of your system is unknown, it's hard to advise you something. But PCI interface between two FPGAs seems to be not very reasonable. It's just spending of resources. It has a sense only if your customer insists on it. There are many more convenient and simpler solutions.

 

[Sink0]

Dear Friends,
My first FPGA have PCI interface with my system and in the second FPGA i have my applications, so i need to transfer the data between the First FPGA which is having PCI interface to the System and the Second FPGA having my application.


Regards,
Kanimozhi.M

As i told you, just create a local 32 bits parallel bus. Take as reference PCI9030 or PCI9052 of PLX. I think that might be the simplest and most reliable solution. The only restriction is that both FPGAs should be as close as possible.

Cya

 

[Mkanimozhi]

Dear Farada,YUV and Sinko,
Thanks for ur replies, But i need to get more clear Can i get ur mail IDs to get more clarification.

Thanks and Regards,
Kanimozhi.M

 

[farhada]

As I said, I can not help you with direct questions, if you send your questions to the list, I will be more than happy to help.
Cheers,
/Farhad

 

[Mkanimozhi]

Ok mam,
I designed the parallel interface between two fpgas, but when i read the data ,the data value is incrementing in the last 4 bits in the 16 bit wide data,how can i slove this problem.

Regards,
Kanimozhi.M

 

[farhada]

Whenever you test a bus, try to do multiple access with different values, then read them back. Your problem sounds like you are reading back the same data but some of the bits of the bus have other sources changing them. This can be due to address conflict, wrong timing on the OE and RD signal among others.

BR,
/Farhad

 

[lucbra]

I would suggest a timing problem. Have you designed the board carefully enough? Is there a negotiation protocol between Tx and Rx?