Need help in interface in verilog - One Clock Pulse?

[digital-newbie]

One Clock Pulse?

I am coding up an interface in verilog that requires me to send an acknowledge pulse signal that remains high for one clock period. I am stuck on how to do this. Any pointers?

 

[gavinsun]

Re: One Clock Pulse?

implementing one level request queue at receving side.
ACK = ~Queue_full & REQ;
Queue_push = REQ & ACK;
Queue_pop = ...

 

[digital-newbie]

Re: One Clock Pulse?

Unfortunately, that does not help me any because I do not have a stack like structure. I am not sure how to generate a pulse that stays high for one clock cycle and goes low again. Any other suggestions would be appreciated. Thanks.

 

[gavinsun]

Re: One Clock Pulse?

Unfortunately, that does not help me any because I do not have a stack like structure. I am not sure how to generate a pulse that stays high for one clock cycle and goes low again. Any other suggestions would be appreciated. Thanks.

Could you show your interface protocol?
such as request, ack,... how they are working?

 

[pintuinvlsi]

One Clock Pulse?

If you are generating the ack signal on some request pos edge, it might be something like this ...

input req;
output ack;
reg req_reg;

always @(posedge clk)
begin
req_reg <= req;
end
assign ack = req & ~req_reg;

 

[AdvaRes]

Re: One Clock Pulse?

I am coding up an interface in verilog that requires me to send an acknowledge pulse signal that remains high for one clock period. I am stuck on how to do this. Any pointers?

You can use a flag for that purpuse !

 

[digital-newbie]

Re: One Clock Pulse?

Thanks for the help guys. I figured it out. The protocol was something like this, I receive a req pulse, perform a read or write operation, then send read data and an ack pulse back after the transaction. The requester, will take in the read data when acknowledge is high. The way I accomplished it was converting that initial request signal into a level using a pulse to level converter, and then when my data is ready, convert that req level back into a pulse, using a level to pulse converter. Level to pulse and pulse to level circuits are very handy and simple. These circuits require a flip flop and an xor gate.