Need help in coding a verilog bi-directional port like this.

[GoldServe]

verilog bidirectional bus

Hi Guys,

I need some verilog coding help. I am trying to write a state machine that accomplishes what the logic trace below does.

USB Data Bus is a bi-directional port
USB Signals are command signals into the chip.
WR# and FRD# are read and write strobes into the chip
JTAG signals are standard JTAG signals out and TDO(IO35) is into the chip

If you look at the trace, you will see that at time t+3.2355hr, FRD# goes low and the bi-directional port changes direction right away and data is outputted onto the data bus. Any help in coding something like this would be helpful!

**broken link removed**

 

[avimit]

bidirectional port verilog

Hi
1. At time t+3.2355hr, FRD is not changing, its WR which is changing
2. I cannot see any indication of direction change of Databus any where in the design, so the Data(?) looks like a unidirectional bus rather than bi-directional bus
3. If you can give me a clear explanation, I would be able to help. I guess its kinda simple to hanlde bi-di bus in vhdl or verilog.
Kr,
Avi
http://www.vlsiip.com

 

[GoldServe]

verilog bidirectional databus

If you look carefully at 3.2355, Cursor E, You will in fact see FRD go low. What baffles me is that when FRD goes low, the Databus gets the value that was shifted out from the previous JTAG cycle so infact the bus is bi-directional. This leads me to believe that the tri-state control of the bus is done by the controller and the tri-state in just hooked up to FRD because there is no delay when FRD goes low to when the data gets put on the Databus.

Please tell me if my assumptions are correct! Thanks!