need help for" Recall the last state"

[chandru4u4]

Hello everyone ,

i am new with vhdl design , i design a one jk flip flop program . here how can initialize "no change" condition .




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jk_ff is
Port ( clock : in STD_LOGIC;
x : inout bit_vector(1 downto 0);
q : inout STD_LOGIC);
end jk_ff;

architecture Behavioral of jk_ff is

begin
process (clock,x)
begin

if (clock = '1')then

case x is
when "01" => q<='0';
when "10" => q<='1';
when "11" => q<='0';
when others => q<=q;
end case;
else

case x is
when "01" => q<='0';
when "10" => q<='1';
when "11" => q<='1';
when others => q<=q;

end case;

end if;
end process;

end Behavioral;

 

[shaiko]

many things are wrong.
lets begin from the beginning.

Why do you define your ports as inout ?
J and K are input only and Q is output only.

your sensitivity list shouldn't have x inside it.
the J and K values are evaluated under the clock edge.

 

[chandru4u4]

thank you for replying , could you please send me correct coding for jk flip flop