oxford
Member level 2
verilog no declare wire
in verilog HDL design, why declare input signals as wire type?
Such as:
-----------------------
module ex1 (a,b,c);
input a;
input b;
output c;
wire a; // why declare 'a' as wire type
wire b; // why declare 'b' as wire type
reg c;
...
----------------------
is there some special reason?
in verilog HDL design, why declare input signals as wire type?
Such as:
-----------------------
module ex1 (a,b,c);
input a;
input b;
output c;
wire a; // why declare 'a' as wire type
wire b; // why declare 'b' as wire type
reg c;
...
----------------------
is there some special reason?