senthilnathan.rajesh
Junior Member level 3
I've written the AES Encryption and Decryption Algorithm (128 bit block and key size) in VHDL. I am implementing this design in a Xilinx Spartan 3E FPGA with ISE 8.1i. Its taking more than an hour to synthesise. I don't know that it takes this much time.
Can the synthesis time be improved.... how...whether there are any synthesis options I've to set...
Can anybody help?
Thanks in Advance.
Can the synthesis time be improved.... how...whether there are any synthesis options I've to set...
Can anybody help?
Thanks in Advance.