native nmos and nmos formation, any difference?

[surreyian]

Hello,

Native nmos has a lower Vth than NMOS. Looking at the layout both device have the same layers. How do we differentiate them in layout?

NMOS is formed from nwell in p-substrate. How about native nmos?

thanks

 

[erikl]

The native nmos gets a (poly-mask defined) low energy (shallow) n^- implant which to some extent compensates the p-substrate doping just below the gate, by this decreases the nMOS V_th -- and increases its "off" leakage current. This implantation is done before gate oxide / poly, of course.

I guess you can't recognize this on silicon, as for those natives the same implant mask openings are used as for their poly gate definitions. The layout, however, must use an individual mask layer. If you can get hold of its layout ...

 

[dick_freebird]

I work in a technology where the native MOS is really intrinsic
silicon, plain epi with no natural dopant. It's still pretty variable,
sensitive to any charging and contamination.

But it's unlikely this is what the original poster is looking at.

Look for things like a non-mask layer that is combined at
mask generation booleans to either counter-dope or flip
gate implant (a zero-VT may also be had by using P+
gate over P- body, where N+ gate would make a positive
VT).