seahs
Newbie level 6
how to include bitline metal layer capacitance in memory design using nanosim?
It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included.
Thanks for any suggestion.
It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included.
Thanks for any suggestion.