N-well antenna effect

[saha.123]

Hi....
Could anyone explain about n-well antenna...How it is different from metal antenna???

Thanks in advance.

 

[anilkrpandey]

N-well antenna is used to remove antenna error in SoC design. Antenna rules are used in SoC design to check for excessive accumulation of charge on metal during fabrication. Antenna error happens when the ratio of area of X, where x can be a metal rout, a local interconnect rout( type of low resistance poly used in some of the processes to do small length connections and voltage distribution like in substrate conn etc.), to the area of gate connected to it increases beyond the FAB mentioned ratio.During IC fabrication, the wafer usually undergoes various processing steps, one of them being etching (to make the surface flat). A typical net in an integrated circuit has a driver (source or drain) which is then connected to a receiver gate electrode over a thin gate dielectric. Now the gate dielectric is so thin that there is always the danger of it getting damaged due to potentials higher than its breakdown potential. This phenomenon is known as antenna effect and the FAB has its own set of rules (which differs with technology node) to avoid such antenna violations while designing the integrated circuit.

 

[quyleanh]

N-well antenna is used to remove antenna error in SoC design. Antenna rules are used in SoC design to check for excessive accumulation of charge on metal during fabrication. Antenna error happens when the ratio of area of X, where x can be a metal rout, a local interconnect rout( type of low resistance poly used in some of the processes to do small length connections and voltage distribution like in substrate conn etc.), to the area of gate connected to it increases beyond the FAB mentioned ratio.During IC fabrication, the wafer usually undergoes various processing steps, one of them being etching (to make the surface flat). A typical net in an integrated circuit has a driver (source or drain) which is then connected to a receiver gate electrode over a thin gate dielectric. Now the gate dielectric is so thin that there is always the danger of it getting damaged due to potentials higher than its breakdown potential. This phenomenon is known as antenna effect and the FAB has its own set of rules (which differs with technology node) to avoid such antenna violations while designing the integrated circuit.

I still cannot get your point. It is seem that your explanation is about metal antenna error.
Could you give more clearly about nwell antenna? (I never heard about them)

 

[rangermad]

The charge build up may not be from the gate to body of the mosfet. It can also be the body to gate of a mosfet. So during processing, before contact and metal, there can be a charge build up on the body of a pmos transistor (nwell) relative to the gate. This is process dependent as anilkrpandey said above. One way to solve the problem, if allowed, is to extend and N+ well tie out into the substrate or pwell. The N+/P diode should provide enough leakage to prevent any damage to the gate oxide.