N channel mosfet Vgd(gate - drain) voltage

[stanislavb]

Hi,
I am interesting some basic question but from my point is not so trivial and it depends from internal structure discrete mosfets.
I am planning to use Mosfet N-channel with following parameter:
Vdsmax = 40V
Vgs = +- 20 V
Result simulation of the circuit give me following results
Vds = 31V
Vgs = 4v
Vgd = -35V(N-channel!)
Once in literature I found that Vgd max voltage higher than Vds max(even significantly larger). And If I exceed Vgd max of course I'll exceed Vdsmax. Nevertheless all above is true depending from internal Mosfet structure. Moreover frustrate me that Vgd is negative but Vds is positive. Shortly speaking do you have idea about relation all these maximum voltage in Discrete N-channel Mosfets
Thank you
Stas

 

[KlausST]

Hi,

Vds = 31V
Vgs = 4v
Vgd = -35V(N-channel!)

V_DS means: Drain_voltage with respect to source_voltage. Use a voltmeter connect the [+] to drain and [-] to source.
equally V_GS
equally V_GD
so it´s not surprising that V_GD is negative. Since the gate voltage is more negative than the drain voltage.

But what surprises me is that the math does not fit.
If V_DS = 31V and V_GS = 4V then V_GD should be -27V.

So far this is nothing specific for a Mosfet or N-channel Mosfet. This is true for any 3 (or more) pole device with pin named "G", "D" and "S". It could be any black box.

***
Sometimes you talk about "max" values and sometimes not. If not "max" then we have to consider them as actually applied DC voltage.
For the "max" values the math does not necessarily need to fit.

Then you talk about a specific Mosfet... please give the link to the datasheet, so we can have a more focussed discussion of the values.

And you talk about a simulation. The same applies here. We need to see the circuit, see how you connected the voltmeters, how you applied the voltage .. then we can give more precise assistance.

"Once in literature I found" .. again here we can´t help you. We don´t know what literature you refer to. If there was a mistake in the document, a missing context, or was it written by a troll.

Klaus

 

[D.A.(Tony)Stewart]

I have never seen what you said in datasheets. Please add a link.

Vgss is often smaller for -ve

This one is an exception.

Drain-Source Voltage VDSS 60 V
Gate-Source Voltage VGSS ±30 V

 

[stanislavb]

Hi,


V_DS means: Drain_voltage with respect to source_voltage. Use a voltmeter connect the [+] to drain and [-] to source.
equally V_GS
equally V_GD
so it´s not surprising that V_GD is negative. Since the gate voltage is more negative than the drain voltage.

But what surprises me is that the math does not fit.
If V_DS = 31V and V_GS = 4V then V_GD should be -27V.

So far this is nothing specific for a Mosfet or N-channel Mosfet. This is true for any 3 (or more) pole device with pin named "G", "D" and "S". It could be any black box.

***
Sometimes you talk about "max" values and sometimes not. If not "max" then we have to consider them as actually applied DC voltage.
For the "max" values the math does not necessarily need to fit.

Then you talk about a specific Mosfet... please give the link to the datasheet, so we can have a more focussed discussion of the values.

And you talk about a simulation. The same applies here. We need to see the circuit, see how you connected the voltmeters, how you applied the voltage .. then we can give more precise assistance.

"Once in literature I found" .. again here we can´t help you. We don´t know what literature you refer to. If there was a mistake in the document, a missing context, or was it written by a troll.

Klaus

Hi,


V_DS means: Drain_voltage with respect to source_voltage. Use a voltmeter connect the [+] to drain and [-] to source.
equally V_GS
equally V_GD
so it´s not surprising that V_GD is negative. Since the gate voltage is more negative than the drain voltage.

But what surprises me is that the math does not fit.
If V_DS = 31V and V_GS = 4V then V_GD should be -27V.

So far this is nothing specific for a Mosfet or N-channel Mosfet. This is true for any 3 (or more) pole device with pin named "G", "D" and "S". It could be any black box.

***
Sometimes you talk about "max" values and sometimes not. If not "max" then we have to consider them as actually applied DC voltage.
For the "max" values the math does not necessarily need to fit.

Then you talk about a specific Mosfet... please give the link to the datasheet, so we can have a more focussed discussion of the values.

And you talk about a simulation. The same applies here. We need to see the circuit, see how you connected the voltmeters, how you applied the voltage .. then we can give more precise assistance.

"Once in literature I found" .. again here we can´t help you. We don´t know what literature you refer to. If there was a mistake in the document, a missing context, or was it written by a troll.

Klaus

Hi,
Thank you for fast reaction!
"If V_DS = 31V and V_GS = 4V then V_GD should be -27V." This is two different situation. When V_GS = 4 V The N-Channel Mosfet is ON and voltage between Drain - Source is almost 0. Therefore V_gd = 4V(because in this case gate voltage is higher then source voltage ); In case Vgs=0, the N-channel is off and V_gd~ -31V(was mistaken when wrote -35V); I am talking about maximum voltage when refer to data sheet parameters. And now what I worried . The maximum V_GS is show us how dielectric between gate and source withstand against high voltage without electrical breakdown. It's clear. However what is about gate-drain. If Mosfet structure is something like serial: Gate - source and source-drain, V_gd will be higher than V_ds. If it's true ,there are no problem in my design because V_ds = 40v and I apply only 31V. If this assumption is not true, what is real maximum V_gd voltage - because there are no any information in data sheet about this parameter
Thank you
Stas

--- Updated Jun 2, 2023 ---

I have never seen what you said in datasheets. Please add a link.

Vgss is often smaller for -ve

This one is an exception.

Drain-Source Voltage VDSS 60 V
Gate-Source Voltage VGSS ±30 V

Thank you for interesting this thread.
It least for power Mosfet Vds maximum is higher than Vgs maximum. But for me interesting how Vgd(Gate - drain) maximum relate to Vgs maximum and Vds maximum. Because I don't see Vgd maximum parameter in datasheet. All above is interesting for N-channel Mosfet. However I presume for P-channel is relevant as well in the same way
Stas

 

[stanislavb]

Hi,
Thank you for fast reaction!
"If V_DS = 31V and V_GS = 4V then V_GD should be -27V." This is two different situation. When V_GS = 4 V The N-Channel Mosfet is ON and voltage between Drain - Source is almost 0. Therefore V_gd = 4V(because in this case gate voltage is higher then source voltage ); In case Vgs=0, the N-channel is off and V_gd~ -31V(was mistaken when wrote -35V); I am talking about maximum voltage when refer to data sheet parameters. And now what I worried . The maximum V_GS is show us how dielectric between gate and source withstand against high voltage without electrical breakdown. It's clear. However what is about gate-drain. If Mosfet structure is something like serial: Gate - source and source-drain, V_gd will be higher than V_ds. If it's true ,there are no problem in my design because V_ds = 40v and I apply only 31V. If this assumption is not true, what is real maximum V_gd voltage - because there are no any information in data sheet about this parameter
Thank you
Stas

--- Updated Jun 2, 2023 ---

Thank you for interesting this thread.
It least for power Mosfet Vds maximum is higher than Vgs maximum. But for me interesting how Vgd(Gate - drain) maximum relate to Vgs maximum and Vds maximum. Because I don't see Vgd maximum parameter in datasheet. All above is interesting for N-channel Mosfet. However I presume for P-channel is relevant as well in the same way
Stas

Hi,


V_DS means: Drain_voltage with respect to source_voltage. Use a voltmeter connect the [+] to drain and [-] to source.
equally V_GS
equally V_GD
so it´s not surprising that V_GD is negative. Since the gate voltage is more negative than the drain voltage.

But what surprises me is that the math does not fit.
If V_DS = 31V and V_GS = 4V then V_GD should be -27V.

So far this is nothing specific for a Mosfet or N-channel Mosfet. This is true for any 3 (or more) pole device with pin named "G", "D" and "S". It could be any black box.

***
Sometimes you talk about "max" values and sometimes not. If not "max" then we have to consider them as actually applied DC voltage.
For the "max" values the math does not necessarily need to fit.

Then you talk about a specific Mosfet... please give the link to the datasheet, so we can have a more focussed discussion of the values.

And you talk about a simulation. The same applies here. We need to see the circuit, see how you connected the voltmeters, how you applied the voltage .. then we can give more precise assistance.

"Once in literature I found" .. again here we can´t help you. We don´t know what literature you refer to. If there was a mistake in the document, a missing context, or was it written by a troll.

Klaus

"Once in literature I found" .. again here we can´t help you. We don´t know what literature you refer to. If there was a mistake in the document, a missing context, or was it written by a troll.

Why Max Vgs rating is there not Vgd in datasheet - Power management forum - Power management - TI E2E support forums

Hi , I am designing a motor driver with mosfets in this regard I am in bit confusion with the below question 1. Why there is max Vgs rating ? 2. Does it indicate

e2e.ti.com

 

[dick_freebird]

Vgs has hard limits and soft limits. Gate rupture is one
you can't get around and will see sandbagged in Abs
Max tables. Hot carrier is a softer long term reliability limit
that likely determines your Rec Max in part. HCE can
incorporate drain bias sensitivity and your Rec Max will
be set by whatever the worst corner may be,

Vds may be punchthrouch / reach-through, or snapback,
or HCE limited.

Vdg -can- have its own special limitations. For example
MOSFETs in heavy ion environments will fail at lower ion
Z when gate voltage is negative (an old timey total dose
mitigation trick) than at zero, as the in-the-moment
potential across oxide is elevated when its shielding
drain-body depletion region collapses along the ion track.
And this is worst at highest (rated) drain potential.

We used to sell MOSFETs of same root P/N rated at
300KRad exclusive of SEE, and only 100K for SEE
environments - thicker gate ox to survive an ion hit, led to
different datasheets. The 100K SEE part would not
support as-large negative gate voltages as part of the deal.

 

[D.A.(Tony)Stewart]

The gate-drain junction is just a small miller capacitance. It is not the modulator of drain-to-source conductance which is Vgs-Vt. Large Negative Vgs is not a desirable design goal. Dick has explained why.

Sure there is a breakdown limit.

But why ask an irrelevant question? (without a link for support)

 

[dick_freebird]

There is a field vector sum at the drain edge which accounts
for lambda and impact ionization. Somewhat variable between
VDMOS (discrete power FET) and LDMOS (integrated power
FET), but never absent.

 

[KlausST]

Hi,

Did you review your post? Hint: when writing a post you may use the "preview".
Even after posting you may edit it. ...for a limited time.

Sadly not much information from your side. Not giving the reqeuested informations at all.

Only one link to a forum discussion. Is this what you call "literature"?

Klaus

 

[stanislavb]

The gate-drain junction is just a small miller capacitance. It is not the modulator of drain-to-source conductance which is Vgs-Vt. Large Negative Vgs is not a desirable design goal. Dick has explained why.

Sure there is a breakdown limit.

But why ask an irrelevant question? (without a link for support)

What you call " irrelevant question"? I am askind what is Vgd limitation for power FET and how estimate it because this parameter is not appear in datasheet?

--- Updated Jun 3, 2023 ---

Hi,

Did you review your post? Hint: when writing a post you may use the "preview".
Even after posting you may edit it. ...for a limited time.

Sadly not much information from your side. Not giving the reqeuested informations at all.

Only one link to a forum discussion. Is this what you call "literature"?

Klaus

I every time review my posts. And lets leave it. This is not literature, but post from forum TI written by TI expert. However, I still want to understand how estimate Vdg because this parameter is not appear in MOSFET datasheets or at least these that I am using
Thank you
Stas

 

[barry]

Youre missing a fundamental issue. If the gate threshold voltage is, say, 6V, and you’ve got 200V on the drain and zero volts on the gate, you’ve got -200V Vgd. So, what’s your point?

 

[stanislavb]

Youre missing a fundamental issue. If the gate threshold voltage is, say, 6V, and you’ve got 200V on the drain and zero volts on the gate, you’ve got -200V Vgd. So, what’s your point?

I want to understand how estimate gate drain voltage limit.
Thank you
Stas

 

[dick_freebird]

Evidently the mfr thinks that the Vds (w/gate condition) and Vgs
(w/ drain condition) "boxes" suffice for reliability. Although down
in the back matter are probably SOA curves and so on, and if a
Vdg concern existed that might be where it's shown (if not said).

Mfr applications engineering would have the golden word on all
this, and you could ask them and report if there's anything, to.

 

[barry]

I have to ask, why are you obsessing about this? If Vg goes more positive than the threshold voltage, Vgd will approximately equal Vgs, as previously pointed out. There are limits specified for max Vgs. If the MOSFET is off, the maximum negative voltage on Vg is limited, again, by the Vgs spec.