My trouble in H.264 decoder design

[hxnudt]

My trouble in H.264 decoder design
I want to implement it in ARM+ASIC:slice header and above is going into SW,my ASIC finish MB header and below .Do you think it work?My trouble is how can i add testbench to my disgn,and is it necessarey to write systemc model, i want to write it in verilog directly.

 

[maverick_mind]

Can you provide more details like what sort of ARM code you have (HDL or SystemC).

Co-simulation may be a tricky task. You may require memory, bus model etc. But I think in modelsim you can co-simulate systemc and HDL models.