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multiported SRAM pass transistors switching delay

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Negneg

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Dear Forum,

I'm trying to calculate the changes in the transistors' switching delay values inside a multiported SRAM. The delay of the bitline, wordline and sense amplifiers are not my interest. I'm only concerned about the delay of the pass transistors and the PMOS and NMOS transistors inside the inverter loop.

My question is if the threshold voltage or size of the transistors change, which affects the switching delay of a transistor, how will it affect the read and write delays?

My thoughts are:
Read -> because the data for first pass transistor connected to Q (inv loop) is already at the gate and the transistor has already been switched on (in the case that Q is '1'), the only delay is the delay of the second pass transistor, which its gate is connected to the wordline. Is this a valid assumption or should I consider both transistors switching delay time?

Write -> the delay is the sum of delay for both pass transistors. Again the delay of the inverters should not be accounted for since the states are already set before the write happens.

Thanks,
 
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