ggeorgak
Newbie level 3
I'm trying to implement a dual processor Microblaze design on my nexys2 fpga. I intend to use the Micron RAM (Micron MT45W8MW16) as a shared memory between both processors.
In order to accomplish that, I need (?) to use a multiport memory controller such as the MPMC IP provided by Xilinx. Unfortunately, trying to configure the IP there is no preset for the particular nexys2 external ram module.
I must add that Micron RAM is a PSRAM device and the nexys2 board support files provided by digilent define the xps_mch_enc IP core as the default memory controller for Micron RAM. Going further, could I use the four channels of the xps_mch_enc IP core to connect the two Microblazes over XCL? Is the memory controller performing the arbitration internally? Also, is there a way to increase the number of channels?
Has anyone managed to solve that?
In order to accomplish that, I need (?) to use a multiport memory controller such as the MPMC IP provided by Xilinx. Unfortunately, trying to configure the IP there is no preset for the particular nexys2 external ram module.
I must add that Micron RAM is a PSRAM device and the nexys2 board support files provided by digilent define the xps_mch_enc IP core as the default memory controller for Micron RAM. Going further, could I use the four channels of the xps_mch_enc IP core to connect the two Microblazes over XCL? Is the memory controller performing the arbitration internally? Also, is there a way to increase the number of channels?
Has anyone managed to solve that?
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