vterminater
Junior Member level 1
Hi i am making a project using VHDL and i wanted to use some low power techniques to optimize my design.
I have used clock gating already.What are the other techniques i can use?
I wanted to implement Multiple Vdd or supply voltages technique.
What are the ways to implement it??
I have heard about Common Power format file(CPF) and UPF files.Can anyone tell me how to use these files or tell me if their is a better way to implement Multiple Vdd.
Thanks
I have used clock gating already.What are the other techniques i can use?
I wanted to implement Multiple Vdd or supply voltages technique.
What are the ways to implement it??
I have heard about Common Power format file(CPF) and UPF files.Can anyone tell me how to use these files or tell me if their is a better way to implement Multiple Vdd.
Thanks