sky_above
Member level 2
There are 10 reg vectors defined in a rtl including two reg outputs of the rtl. The name of the reg vectors are reg1, reg2, reg3, reg4, reg5 ....There is a if-else statement in the rtl inside a combinational always block. When the first expression of the if-else statement evaluates true only the first reg named reg1 of the 10 reg vectors need to be assigned a new expression and other reg are not needed to be assigned new expressions. When the second expression of the if-else statement evaluates true only the second reg named reg2 of the 10 reg vectors need to be assigned a new expression and other reg are not needed to be assigned new expressions. So will the assignment for reg2, reg3, reg4... be as below for the first expression of the if-else statement or they need not be mentioned in the first expression of the if-else statement ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 if (expression1) reg1 = a+b; reg2 = reg2; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... else if ( expression2 ) reg1 = reg1; reg2 = c-d; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... ............... ...............
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