kil
Member level 5
asic multicycle path for different clock domains
Hi All,
How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage DC tool it self will recognize and through as warning or error.
At what stage in the asic flow this multicycle path and False path are identified. How to fix this Multi cycle path and false path in the asic fpga flow
How it is going to effect the Timing Closure and the Slack of the design.
regards
kil
Hi All,
How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage DC tool it self will recognize and through as warning or error.
At what stage in the asic flow this multicycle path and False path are identified. How to fix this Multi cycle path and false path in the asic fpga flow
How it is going to effect the Timing Closure and the Slack of the design.
regards
kil