cafukarfoo
Full Member level 3
Hi everyone,
Can anyone explain in details for statement below.
"multibank architecture allow for concurrent operation to enable to hide row precharge/activation time"
I wonder how can i write concurrently because DDR SDRAM only have single DQS, DQ and control signal such as we, ras, and cas.
Thanks in advance for your help.
Can anyone explain in details for statement below.
"multibank architecture allow for concurrent operation to enable to hide row precharge/activation time"
I wonder how can i write concurrently because DDR SDRAM only have single DQS, DQ and control signal such as we, ras, and cas.
Thanks in advance for your help.