Multi core FPGA? Timing problems

[Kuller]

multicore fpga spartan

Hi,

I am having some trouble with the Xilinx implementation. The thing is that I have two different projects that fits directly into the same FPGA sharing the clock. One of them can run up to 150 MHz and the other one up to 70 MHz.

The problem is if I constraint the clock for 150 MHz it doesnt let me to implement the design as the slow core has a path delay bigger than 6 ns. I dont really care about this as I know that it is not going to be used at more than 70 MHz but the implementatin fails.

My configuration is: (same constraint for both clocks, doesnt work)
IOB->DCM->core1
|-> core2

I have tried too: (same as before)
IOB->DCM1->core1
|-> DCM2->core2

And:
IOB->DCM1->core1 ( ologic problem but I can get 2 different clock nets)
|->DDR FF->DCM2->core2

I tried to put a from, to constraint ( It didnt work )

Is there anyway to split 1 clock into two fully independent clocks?

I am really stuck at this moment :/

Thanks

 

[echo47]

I haven't found an easy way to specify different PERIOD constraint to two parts of the same clock net. You could probably apply grouping constraints to your two cores, and then apply different FROM-TO timing constraints to the two groups, but I find the grouping process to be a nightmare. Maybe there's an easy way to do grouping that I haven't discovered.

If you don't mind wasting a global clock buffer, you could instantiate two BUFG's (or BUFGMUX's), both driven by the same clock pin, and then apply different PERIOD constraints to the BUFG outputs. That seems to work. Here's a Spartan-3 example with one master clock input split into two differently constrained clock nets - one feeds a fast module (32-bit arithmetic), the other feeds a slow module (80-bit arithmetic):

module top (clk, out_slow, out_fast);
  input         clk;
  wire          clk_slow, clk_fast;
  output        out_slow, out_fast;

  BUFG buf1 (.I(clk), .O(clk_slow));
  BUFG buf2 (.I(clk), .O(clk_fast));

  core_slow core1 (.clk(clk_slow), .out(out_slow));
  core_fast core2 (.clk(clk_fast), .out(out_fast));
endmodule


module core_slow (clk, out);
  input         clk;            // synthesis attribute PERIOD clk "70 MHz";
  reg    [79:0] count = 0;
  output reg    out = 0;

  always @ (posedge clk) begin
    count <= count + 1;
    out   <= ^count;
  end
endmodule


module core_fast (clk, out);
  input         clk;            // synthesis attribute PERIOD clk "150 MHz";
  reg    [31:0] count = 0;
  output reg    out = 0;

  always @ (posedge clk) begin
    count <= count + 1;
    out   <= ^count;
  end
endmodule

 

[Kuller]

Thank you, this was really what I was looking for.

I have tried it and works like a charm