Vimala04
Newbie level 2
can you plz explain the flow of this code?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module(clk,mpulse,speed); input clk,mpulse; output[15:0]speed; wire [15:0]speed; reg[31:0]cval, tcount, quot,rem; reg zero,sts; wire rfd; assign speed = (zero?16'd0:quot[15:0]); always@(posedge clk) begin if(!mpulse && sts) begin tcount = cval; sts = 1'b0; cval = 32'd0; zero = 1'b0; end else begin if(mpulse) sts = 1'b1; if(cval = 32'd4000000) zero = 1'b1; else cval = cval+32'd1; end end spddiv speeddiv(.dividend(32'd120000000), .divisor(tcount), .quot(quot, .rem(rem), .clk(clk), .rfd(rfd)); endmodule
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