whedaboard
Newbie
Hi there.
I have a confusion with the locking ability of very low bandwidth PLL/FreqSynthesizer:
Talking about a Type-2 PLL, consisting of PFD, ChargePump, 2nd-order LPF ((R+C1)//C2), VCO and N-divider (let's assume N=1 for simplicity).
If we design the PLL bandwidth very very low, to tolerate the high input jitter, or in the case of a Clock-Recovery PLL which has extremely low loop bandwidth to tolerate the occasional "11" or "00", then we have to have very very low loop gain to make the loop stable (enough phase margin in open loop transfer function) due to the open loop transfer function.
However, if we want to have a very low loop gain, given that Kvco and PFD gain are probably inflexible, the only freedom in design is the charge pump current Icp. If we have a very small Icp, then locking range of the PLL will be very small, because the the loop is so weak that it doesn't have enough gain to pull the VCO to the target locking frequency.
Then I'm wondering, how can these kinds of very low bandwidth PLL even work/lock? I know there're techniques like AFC, which sweeps the Vctrl of VCO and limits the Vctrl within a small voltage range to assist lock. But does it mean if I don't use assisting technique, the loop by itself just simply won't work?
I have a confusion with the locking ability of very low bandwidth PLL/FreqSynthesizer:
Talking about a Type-2 PLL, consisting of PFD, ChargePump, 2nd-order LPF ((R+C1)//C2), VCO and N-divider (let's assume N=1 for simplicity).
If we design the PLL bandwidth very very low, to tolerate the high input jitter, or in the case of a Clock-Recovery PLL which has extremely low loop bandwidth to tolerate the occasional "11" or "00", then we have to have very very low loop gain to make the loop stable (enough phase margin in open loop transfer function) due to the open loop transfer function.
However, if we want to have a very low loop gain, given that Kvco and PFD gain are probably inflexible, the only freedom in design is the charge pump current Icp. If we have a very small Icp, then locking range of the PLL will be very small, because the the loop is so weak that it doesn't have enough gain to pull the VCO to the target locking frequency.
Then I'm wondering, how can these kinds of very low bandwidth PLL even work/lock? I know there're techniques like AFC, which sweeps the Vctrl of VCO and limits the Vctrl within a small voltage range to assist lock. But does it mean if I don't use assisting technique, the loop by itself just simply won't work?