[moved] D-flipflop freq divider initial phase

[AllenD]

Hi All,
I am using a Hybrid Latch Flip-Flop (HLFF) circuit work as a D-flipflop, and feedback from Q_b to D to realize a freq divide by 2 circuit.

My question is how to regulate the initial phase?
In the attached pic on the left is the HLFF with reset and feedback. On the right:
1. Blue is the reset signal.
2. For the red group, the signals are D, CLK, Q in order (the first line is D, the second line is CLK and the third line is Q ). Same for the Green group
3. The difference of red and green is that I use a different transistor from PDK to simulate the exact HLFF circuit topology.
You can see in both cases, the CLK signal (the 2nd and 5th signal in plot) of red and green are the same. But the difference is the starting phase of the output. For red, Q rise with the 3rd, 5th, and 7th rising edge of CLK but in green, Q rise with the 2nd, 4th, and 6th rising edge of CLK.
As result, the Q of red and green are the opposite.
Can you please let me know how to prevent this phenomenon?
Thanks
Al

 

[barry]

The thing that immediately jumps out at me is that as soon as the reset is de-asserted, the green Q output changes. There's something wrong there. Is the reset supposed to be asychronous? If it's synchronous there might be a timing issue.

I once had a situation where I was de-asserting the asynchronous reset too close to the clock edge, which erroneously caused the Q output to change. The manufacturer traced the glitch down to a particular fab facility. Only devices from a particular fab exhibited this behavior.

 

[AllenD]

The thing that immediately jumps out at me is that as soon as the reset is de-asserted, the green Q output changes. There's something wrong there. Is the reset supposed to be asychronous? If it's synchronous there might be a timing issue.

Thanks for your reply. I plan to add a switch off-chip to manually reset the IC. So I pick the reset signal phase randomly. Can you please elaborate on "synchronous "? synchronous to whom? If you mean for the case of red and greed, the blue reset signal is identical for both red and green cases.

--- Updated Dec 10, 2020 ---

The thing that immediately jumps out at me is that as soon as the reset is de-asserted, the green Q output changes. There's something wrong there. Is the reset supposed to be asychronous? If it's synchronous there might be a timing issue.

I once had a situation where I was de-asserting the asynchronous reset too close to the clock edge, which erroneously caused the Q output to change. The manufacturer traced the glitch down to a particular fab facility. Only devices from a particular fab exhibited this behavior.

Hi!, I found this..... It seems interesting! Thanks for mentioning this potential problem to me!

Asynchronous reset synchronization and distribution – challenges and solutions - Embedded.com

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we

www.embedded.com

 

[barry]

"synchronous to whom?" Synchronous to your clock.

 

[AllenD]

"synchronous to whom?" Synchronous to your clock.

Yes you are right. I delayed the reset by 0.2 clk period and both red and green case synchronized..... I guess I need to find a way to, as you suggested, Synchronous to the clock. Can you please recommend any circuit to achieve it? Just the name or keywords would be immensely helpful.

 

[barry]

I'm not quite sure you're doing here. Are you building a flip-flop out of discrete transistors? Designing a chip?

Regardless, look up "synchronous reset". But, do you actually WANT synchronous reset and not ASYNCHRONOUS reset?