kvidhya
Newbie level 5
Good after noon
i am facing a problem in analog layout
i design one layout
it is d.r.c and l.v.s cleared
when i am calling that same design it is creating some errors
i checked the file weather any file locks are present but no such locks
can any one help in this problem
i am facing a problem in analog layout
i design one layout
it is d.r.c and l.v.s cleared
when i am calling that same design it is creating some errors
i checked the file weather any file locks are present but no such locks
can any one help in this problem