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Monitoring the signal in VHDL Test bench

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rocking1234

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Hi

In VHDL is there any way to monitor the signal as we do in verilog to watch internal signal rather than looking at the waveform.

Also could any1 suggest for VHDL test bench creator,
I mean I need to write
1 : a VHDL test ench and intialise some test case
2 : monitor the DUT values
3 : compare the DUT value with expected cases

Is it possible to perform all in VHDL Test bench.....?
 

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